Design engineers have long been familiar with USB, first introduced in 1995 to replace the aging RS232 interface. It represents a simple, elegant means of communicating with as many as 126 connected devices using a well-defined protocol.
However, adding USB to an existing product is not necessarily simple or elegant, and adding it to new projects adds a degree of complexity that may now be largely avoidable.
Cypress Semiconductor’s CY8C24794-24LFXI is a member of its popular Programmable System-on-Chip (PSoC) family of mixed-signal arrays. The 24794 includes a full-speed (12 Mbps) USB 2.0 Serial-Interface Engine (SIE), including a 0.25 percent accurate clock with an integrated oscillator that meets USB 2.0 clocking specifications and requires no external crystal, reducing component and pin counts. The device offers PSoC designers a complete USB interface, essentially for free.
The CY8C24794 provides four unidirectional endpoints and one bi-directional control endpoint to support control, interrupt, isochronous, and bulk transfer types, as well as flexible synchronization. It offers up to 48 analog inputs, so no external analog multiplexer is required for applications such as laptop touchpads using CapSense technology. This article describes the new PSoC, its USB interface and applications that can be easily designed using the device.
Not Your Father’s SoC
The PSoC family of devices are designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of pin-outs and packages. The PSoC CY8C24794 is a unique member of the PSoC family because it includes a full-featured, full-speed (12 Mbps) USB port.
The PSoC architecture (Figure 1) consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24794 device can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks.
The PSoC core consists of a 24-MHz, 4-MIPS Harvard-architecture CISC CPU with 16-Kbits of Flash for program storage, 1-Kbit of SRAM for data storage and up to 2Kbits of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low-speed oscillator (ILO) is provided for the Sleep timer and watchdog timer (WDT).
PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may beselected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System (Figure 2) is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees designs from the constraints of a fixed peripheral controller.
The Analog System (Figure 3) consists of six configurable blocks, each comprised of an op amp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Analog blocks are arranged in a column of three, which includes one Continuous Time (CT) and two Switched Capacitor (SC) blocks.
The CY8C21x34 and CY8C24x94 PSoC devices differ from the other PSoC devices in that GPIO pins can connect to the internal analog bus. The CY8C24x94 contains the additional capability to optionally split the analog bus into two separate sections. In the CY8C21x34 all GPIO pins are enabled for this connection. In the CY8C24x94 all pins in Ports 0 through 5 are enabled for connection to the analog Bus.
System Resources provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset.
The PSoC USB system resource adheres to the USB 2.0 specifications for full-speed devices operating at 12 Mb/second with one upstream port and one USB address. PSoC USB (Figure 4) consists of a Serial Interface Engine (SIE) block; a PSoC Memory Arbiter (PMA) block; 256 bytes of dedicated SRAM; a Full-Speed USB Transceiver with internal regulator; and two dedicated USB pins.
At the system level, the full-speed USB system resource interfaces to the rest of the PSoC by way of the M8C’s register access instructions and to the outside world by way of the two USB pins.
The SIE supports five endpoints including a control endpoint (endpoint 0) and four data endpoints (endpoint 1, 2, 3, and 4). The control endpoint can be configured to support SETUP, IN, and OUT requests. The data endpoints can be individually configured to respond to Interrupt, Bulk, or Isochronous IN or OUT requests.
The USB Serial Interface Engine (SIE) allows the PSoC device to communicate with the USB host at full-speed data rates. The SIE simplifies the interface to USB traffic by automatically handling the following USB processing tasks without firmware intervention:
• Translating the encoded received data and format the data to be transmitted on the bus.
• CRC Checking and Generation. Incoming packets failing checksum verification are ignored.
• Address Checking. Ignores all transactions not addressed to the device.
• Sending appropriate ACK/NAK/Stall handshakes.
• Identifying token type (SETUP, IN, OUT) and setting the appropriate token bit once a valid token in received.
• Identifying Start-of-Frame (SOF) and saving the frame count.
• Sending data to or retrieving data from the USB SRAM, by way of the PSoC Memory Arbiter.
Firmware is required to handle various parts of the USB interface. The SIE issues interrupts after key USB events to direct firmware to appropriate tasks: fill and empty the USB data buffers in USB SRAM; enable PMA channels appropriately; coordinate enumeration by decoding USB device requests; suspend and resume coordination; verify and select data toggle values.
The PSoC USB System Resource contains a dedicated 256 byte SRAM. This SRAM is identical to an SRAM page used in the PSoC Core; however, it is not accessible by way of the M8C memory access instructions. The PSoC USB’s dedicated SRAM may only be accessed by way of the PMA registers.
The PSoC Memory Arbiter (PMA) is the interface between the PSoC USB’s dedicated SRAM and the two blocks that access the SRAM: the M8C and the USB SIE. The PMA provides eight channels to manage data. All of the channel registers may be used by the M8C, but the four non-control USB endpoints are each allocated to a specific set of PMA channel registers. The internal USB transceiver interfaces to the external USB bus to transmit and receive signals according to the USB 2.0
Specification. In normal USB operation, the transceiver interfaces directly to the SIE and no user interaction is needed after initialization.
Connecting to an external USB device is simple, requiring only the addition of two resistors. Figure 5 shows a sample schematic for USB with the 56-pin MLF PSoC device (CY8C24794).
The CY8C24794-24LFXI includes Cypress’ CapSenseTM technology, which offers an efficient solution to replace mechanical switches and controls with simple, touch-sensitive controls. The PSoC architecture makes it easy to connect touch-sensitive controls to LED drivers, LCD displays and other peripherals.
In its basic form, a capacitive switch is a pair of adjacent plates, as shown in Figure 6a. There is a small edge-to-edge capacitance, but the intent of switch layout is to minimize the capacitance between these plates. When a conductive object is placed in proximity to the two plates, as shown in Figure 6b, there is a capacitance between one electrode and the conductive object and a similar capacitance between the conductive object and the other electrode.
The most common form of capacitance switch array is a set of capacitors where one side of each is grounded. Thus, the active capacitor has only one accessible side; the switch is a grounded variable capacitor. The presence of the conductive object increases the capacitance of the switch to ground. Determining switch activation is then a matter of measuring change in the capacitance.
The CY8C21x34 family has unique features that enable efficient designs for capacitive switch scan applications. The features include wide multiplexer array so that all channels being measured can be serviced by a common comparator and current source; a DAC adjustable current source; and automatic connection of comparator and reset switch.
This drive and multiplex arrangement bypasses the existing GPIO to connect the selected pin to an internal Analog Mux Bus, as shown in Figure 7. The capacitor charging current (IDAC, controlled by register DAC_D) and reset switch are connected to the Analog Mux Bus. This limits the pin-count requirement to simply the number of switches to be addressed; no external resistors or capacitors are required to enable operation.
The basic circuit and firmware of the PSoC CapSense solution are relatively simple, the physical design of the switchoperating environment is less so. There are three major categories for consideration when designing with capacitive sensing: the printed circuit board (PCB), the overlay material, and other elements not related to the PCB or capacitive sensing. Cypress has a series of application notes that cover these areas in more detail than we can manage here.
Example: Buttons and Lights
The CY8C24794 is supported by PSoC DesignerTM software, an evaluation board, ICE-Cube in-circuit emulator and miniprogrammer, all of which make it easy to experiment with new designs. The basic USB-based design described here lets you press a button on your target host PC and light up lights on the evaluation board. With all USB designs you are always dealing with two programs: one in the host and one in the remote device. A USB device does not actually ‘send’, it prepares data that the USB host will come and collect; the host controls all communications and a device only ‘talks’ when the host permits it.
The flow chart in Figure 8 shows the logical operation of the programs in both the device and the host in our example:
The USB_Start() call initiates the enumeration sequence that is handled by the USB User Module libraries; once enumeration is completed, we then post a buffer to receive a lights report from the PC. We then wait for an SOF flag to be set. The SOF_ISR sets this flag every 1 msec.
Once the SOF flag is set, we call scan-buttons(), which is a button de-bouncing routine. If we detect a button change, then we send a buttons report to the PC. We then check to see if a lights report was received in the previous frame; and, if so, we update the local LEDs. Note that from main()’s perspective, data is moved into and out of endpoint buffers; USB communications are handled in the background by the SIE. The USB run-time operation is as simple as reading and writing endpoint buffers.
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